1. Field of the Invention
The present invention pertains to the field of computer systems. More particularly, this invention relates to a mechanism for stalling an in-order instruction fetch pipeline during instruction stream repairs in an a processor performing speculative out-of-order instruction execution.
2. Background
Typical prior computer processors implement in-order instruction execution pipelines. An in-order processor usually fetches an instruction stream from a memory, and executes each instruction in the instruction stream according to a sequential program order. Such in-order instruction execution ensures that data dependencies among the instructions are strictly observed.
A processor may perform out-of-order instruction execution to increase instruction execution performance. Such a processor executes ready instructions in the instruction stream ahead of earlier instructions in the program order that are not ready. A ready instruction is typically an instruction having fully assembled source data and available execution resources.
Such out-of-order execution improves processor performance because the instruction execution pipeline of the processor does not stall while assembling source data or execution resources for a non ready instruction. For example, a non ready instruction awaiting source data from an external memory fetch does not stall the execution of later instructions in the instruction stream that are ready to execute.
A processor may also perform speculative instruction execution to increase instruction execution performance. Such a processor typically determines a speculative execution path through a program by predicting the result of branch instructions. Such a processor fetches an instruction stream from a memory, predicts a branch result for each branch instruction, and continues fetching and executing the instruction stream according to the predicted branch result. Such speculative execution increases processor performance because the instruction fetch and execution pipeline does not stall during the resolution of branch instructions.
A processor that performs both speculative and out-of-order instruction execution generates speculative result data in an out-of-order sequence in relation to the original program order. The result data is out-of-order because the instructions that cause generation of the result data are executed out-of-order. The result data is speculative until the branch predictions that caused speculative execution of the instructions are resolved.
A processor that performs speculative instruction execution typically fetches an instruction stream down an incorrect program path if a branch instruction is mispredicted. As a consequence, the internal registers and execution resources of such processors become corrupted with invalid instructions and result data. Such processors require a mechanism for removing the invalid instructions and invalid result data, and for redirecting the instruction stream to the proper program path after a branch misprediction.
Prior processors that perform speculative execution typically employ multiple sets of internal registers to hold speculative information for each branch prediction. Such a processor allocates one the internal register sets to each speculative execution path. The invalid instructions and result data for a mispredicted branch are removed by clearing the corresponding internal register set and switching to an internal register set for the program path prior to the mispredicted branch.
Unfortunately, the implementation of multiple sets of internal registers increases manufacturing costs for such processors because each register set increases the integrated circuit die space for the processor. As a consequence, such processors are typically limited to a small number of internal register sets, thereby limiting the number of program nesting levels that can be speculated.